1. Technical Field
Embodiments exemplarily described herein relate generally to semiconductor devices and more particularly to a metal wiring of a semiconductor device and a method for fabricating the same.
2. Description of the Related Art
Highly integrated semiconductor devices are becoming more miniaturized and lighter in weight. As a result, the design rule of semiconductor devices is becoming more reduced. As the design rule is reduced, a width of a metal wiring is also narrowed and it becomes complicated to form via contacts for connecting lower wirings and upper wirings.
Semiconductor devices are fabricated by stacking and patterning a plurality of films or layers on a semiconductor substrate. Above all, an alignment between films or layers is a critical factor. An overlap margin between a lower wiring and an upper wiring, which are electrically interconnected to each other, may be sufficiently considered when a contact hole pattern is disposed to electrically connect films or layers of a semiconductor device.
It can be desirable to secure a maximum overlap margin at a layout in order to perform a stable process. With current trends, however, the contact hole overlap margin becomes minimized due to the high integration of semiconductor devices. In particular, some products or processes have been made or executed without the overlap margin.
FIGS. 1A to 1C are cross-sectional views illustrating a metal wiring fabricating method of a semiconductor device according to the prior art.
Referring to FIG. 1A, a lower interlayer insulating layer 14 with a metal pattern 12 is formed on a semiconductor substrate 10, and an upper interlayer insulating layer 16 is formed on the lower interlayer insulating layer 14. Lower metal wirings 20 are formed on given regions of the upper interlayer insulating layer 16. An interlayer insulating film 22 is formed to cover the lower metal wirings 20. The interlayer insulating film 22 is flattened by use of a well-known chemical mechanical polishing manner.
Referring to FIG. 1B, a photoresist pattern 28 is formed on the flattened interlayer insulating film 22 so as to expose the interlayer insulating film 22 on the lower metal wirings 20. In order to expose upper surfaces of the lower metal wirings 20, via holes 30 are formed by etching the exposed interlayer insulating film 22 using the photoresist pattern 28 as a mask.
Referring to FIG. 1C, after removing the photoresist pattern 28, via contacts 35 are formed to fill the via holes 30, and upper metal wirings 40 are respectively formed on the via contacts 35 so as to be connected electrically to the lower metal wirings 20.
FIG. 2 is a cross-sectional view illustrating a problem of a metal wiring of a semiconductor device according to the prior art.
Referring to FIG. 2, in a case where a metal wiring of a semiconductor device is formed using processes described in FIGS. 1A to 1C, misalignment can occur when forming the via holes 30. This misalignment makes the interlayer insulating film 22 at edges of the lower metal wirings 20 be etched during an etching process for forming the via holes 30. Accordingly, the upper metal wirings 40 are electrically interconnected with a region that must be insulated (i.e., metal pattern 12) as well as with the lower metal wirings 20.
In the case that a metal wiring of a semiconductor device is formed in the above-described manner without the overlap margin, such misalignment can occur during a via hole forming process for connecting the lower metal wirings 20 and the upper metal wirings 40. For this reason, via holes may be formed on upper surfaces of the lower metal wirings 20 and at edges thereof. The upper interlayer insulating layer 16 below the lower metal wirings 20 is simultaneously etched when etching the interlayer insulating film 22 to form via holes. As a result, an electrical interconnection between a lower metal wiring and a metal pattern which is to be insulated and is undesirably formed below the lower metal wiring.